By Per Stenström, David Whalley
ISBN-10: 3642009034
ISBN-13: 9783642009037
ISBN-10: 3642009042
ISBN-13: 9783642009044
Transactions on HiPEAC goals on the well timed dissemination of study contributions in machine structure and compilation equipment for high-performance embedded desktops. spotting the convergence of embedded and general-purpose computers, this magazine publishes unique learn on structures distinct at particular computing initiatives in addition to structures with large program bases. The scope of the magazine for that reason covers all facets of desktop structure, code iteration and compiler optimization equipment of curiosity to researchers and practitioners designing destiny embedded systems.
This moment factor comprises 15 papers rigorously reviewed and chosen out of 31 submissions and is split into sections. the 1st part includes prolonged models of the pinnacle 5 papers from the 2d overseas convention on High-Performance Embedded Architectures and Compilers (HiPEAC 2007) held in Ghent, Belgium, in January 2007. the second one part involves ten papers masking subject matters equivalent to microarchitecture, reminiscence platforms, code iteration, and function modeling.
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Additional resources for Transactions on High-Performance Embedded Architectures and Compilers II
Sample text
Ciphertext read from the off-chip memory is decrypted by the following operation performed on-chip: p = c ⊕ Encrypt(K, Addr + Counter). The off-chip memory is augmented with additional memory locations where the actual counter value used during encryption of data is stored. Thus, the counter value can be fetched along with the data so that decryption can be performed. However, doing so causes load latency to increase because computation of onetime-pad cannot be performed until the Counter value has been fetched.
Edu Abstract. A critical component in the design of secure processors is memory encryption which provides protection for the privacy of code and data stored in off-chip memory. The overhead of the decryption operation that must precede a load requiring an off-chip memory access, decryption being on the critical path, can significantly degrade performance. Recently hardware counter-based one-time pad encryption techniques [13,16,11] have been proposed to reduce this overhead. For high-end processors the performance impact of decryption has been successfully limited due to: presence of fairly large on-chip L1 and L2 caches that reduce off-chip accesses; and additional hardware support proposed in [16,11] to reduce decryption latency.
Nagarajan, R. Gupta, and A. Krishnaswamy sharing optimizations contribute significantly although intraprocedural sharing contributes more than across-procedure sharing. In Table 3 the number of counter-ids used with and without sharing are given. In addition, the number of counters used with sharing as a percentage of counters needed without sharing, is also given. , we have roughly 2 fold reduction). Note that Intraprocedural sharing does not cause reduction in counter-ids. Although the counter-ids do not represent a hardware resource, reducing the number of counter-ids is beneficial as the size of counter-id allocated can be reduced.
Transactions on High-Performance Embedded Architectures and Compilers II by Per Stenström, David Whalley
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