By Bradly K. Fawcett
ISBN-10: 0139837426
ISBN-13: 9780139837425
A close learn of the 16-bit microprocessor emphasizing common sense layout with the Z8001 and Z8002 microprocessors. different parts within the Z8000 kin of components are mentioned. worthwhile to an individual drawn to studying in regards to the Z8000 who has had a few adventure with microprocessors and understands techniques corresponding to registers, buffers, software counters, and interrupts.
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Additional resources for The Z8000 microprocessor: A design handbook
Sample text
Z6132 (ODD) Memory Refresh 47 words of random access data/stack memory. The program memory address space consists of two 2K X 8 2716 erasable programmable read-only memories (EPROMs). The data and stack memory space is shared by two Z6132 4K X 8 RAMs. Since program memory accesses are differentiated from data and stack accesses in this example, the STO-ST3 lines are used as part of the chipselect logic. A 74LS42 4-to-16 decoder is used to decode the status lines. IF1 or IFn status (that is, any instruction fetch) will activate the chip enable (CE) inputs of the 2716 EPROMs; since accesses to EPROMs are always reads, both byte banks of EPROMs are activated each time program memory is accessed.
Q. ~ NO REFRESH --f- 6 u.. I Z a:: w Q. Q. 20 Refresh period in clock cycles. counter and setting bit 15. 20 shows the relationship between the value loaded into the upper byte of the refresh register and the number of clock cycles between each refresh. For example, loading a 9EOO into the refresh register means that a refresh will be generated every 60 clock cycles (every 15 I1S in a. 4-MHz system, which is adequate to satisfy the worst-case refresh requirements of typical 16K RAMs). When reading the refresh register using the LDCTL instruction, only the row counter portion (bits 0-8) of the register can be read.
The original starting count is automatically reloaded after the counter reaches O. Loading a starting count of zero provides the longest possible period between refresh cycles: 64 X 4 X the clock period. During a refresh cycle, the row counter in the refresh register is output on ADO-AD8, and the ST3-STO status lines are set to 0001. Since memory in Z8000 systems is word organized, and ADO is used only to distinguish bytes within a word, ADO is not considered part of the memory's row address, and is always 0 in the refresh register.
The Z8000 microprocessor: A design handbook by Bradly K. Fawcett
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