By Vojin G. Oklobdzija et al.
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Extra resources for The Computer Engineering Handbook
Example text
Two 1-bit outputs are the Sum and the Carry-Out. The outputs can be represented by the equations: Sum = ABC + AB′C ′ + A′B′C + A′BC′ and Carry-Out = AB + AC + BC = AB + (A + B)C [9]. The implementation of this circuit requires 14 NMOS and 14 PMOS transistors. Pseudo-NMOS Logic Pseudo NMOS is a ratioed logic. That is for the correct operation of the circuit the width-to-length ratios (W/L s) of the transistors must be carefully chosen. Instead of a combination of active pulldown and pull-up networks, the ratioed logic consists of a pull-down network and a simple load device.
145–148, 1999. 30. Y. Ma, Y. Ono, L. Stecker, D. R. Evans, and S. T. 0 nm and performance of submicron MOSFET using a nitride gate replacement Process,” IEDM Tech. , pp. 149–152, 1999. 31. -J. Qi, R. Nieh, B. H. Lee, K. Onishi, L. Kang, Y. Jeon, J. C. Lee, V. -Y. Nguyenl, L. Prabhul, K. Eisenbeiser, and J. Finder, “Performance of MOSFETS with ultra thin ZrO2 and Zr-silicate gate dielectrics,” Symp. , Dig. , pp. 40–41, June, 2000. 32. L. Kang, Y. Jeon, K. Onishi, B. H. -J. Qi, R. Nieh, S. Gopalan, and J.
In Fig. 7, the output value is equal to 0 when either A or B is equal to 1 because one of the NMOS transistors will be ON. But if both inputs are equal to 0, the series pair of PMOS transistors between VDD and the output Y will be ON, resulting in a 1 at the output, which is the desired functionality of a NOR gate. 8 illustrates a 2-input CMOS OR gate realized in two different fashions. In the first method, an inverter is connected to the output of a NOR circuit to obtain an OR circuit. In the second method, we make use of DeMorgan’s theorem, (A′B′)′ = A + B, to realize the OR logic function.
The Computer Engineering Handbook by Vojin G. Oklobdzija et al.
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