By Mingsong Chen
ISBN-10: 1461413583
ISBN-13: 9781461413585
ISBN-10: 1461413591
ISBN-13: 9781461413592
This publication covers state-of-the paintings suggestions for high-level modeling and validation of complicated hardware/software platforms, together with people with multicore architectures. Readers will discover ways to steer clear of time-consuming and error-prone validation from the excellent assurance of system-level validation, together with high-level modeling of designs and faults, automatic new release of directed checks, and effective validation technique utilizing directed assessments and assertions. The methodologies defined during this ebook may help designers to enhance the standard in their validation, acting as a lot validation as attainable within the early phases of the layout, whereas decreasing the final validation attempt and cost.
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Extra info for System-Level Validation: High-Level Modeling and Directed Test Generation Techniques
Sample text
If the SAT problem is satisfiable, it means that the property is false and a counterexample of the property will be reported. SAT-based BMC can not only generate counterexamples much faster than traditional BDD-based model checking, but also the generated counterexample is of shorter length which can locate the design bug quickly. The rest of this chapter is organized as follows. 2 introduces the related work on various SoC validation approaches including model checking based techniques. 3 presents the workflow of directed test generation approach using model checking.
2b shows the graph representation of its corresponding formal model. In the graph model, each circle (node) is called a place that is used to indicate the input or output buffer of a module. It can temporarily hold the transaction data for later processing. The edges (vertical bars with incoming and outgoing arrow lines) are transitions, which are used to indicate modules that contain processes to manipulate input and output transaction data tokens. The places 24 2 Modeling and Specification of SoC Designs (b) (a) t1 M5 M1 t5 t3 M3 t6 t2 M2 M6 t4 M4 Fig.
Chapter 8 [Test Generation using Design and Property Decompositions]. To alleviate the state space explosion problem, this chapter presents promising design and property decomposition techniques to reduce the test generation time. Chapter 9 [Learning-Oriented Property Decomposition Approaches]. To simplify the subtest composition process in Chap. 8, this chapter presents a fully automated test generation approach based on the property decomposition and decision ordering based learning techniques.
System-Level Validation: High-Level Modeling and Directed Test Generation Techniques by Mingsong Chen
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