By David L. Weaver
ISBN-10: 0557019745
ISBN-13: 9780557019748
"OpenSPARC Internals: OpenSPARC T1 and T2 Chip Multithreaded (CMT) Throughput Computing" presents an creation to the open-source OpenSPARC T1 and T2 microprocessors. OpenSPARC T1 and T2 are the 1st and basically open-source CMT (Chip Multi-Threaded) microprocessors and primary and in basic terms open-source 64-bit microprocessors in lifestyles. an entire T1 layout includes eight cores (32 threads), whereas T2 is eight cores (64 threads). This publication comprises an summary of the way OpenSPARC may be placed to educational or commerical use, establishing improvement atmosphere, reconfiguring the deisgns to differing numbers of threads or cores, synthesizing OpenSPARC T1 into FPGA recommendations, configuring/using OpenSPARC simulation software program, compiling software program for an OpenSPARC goal processor, and a few dives into the OpenSPARC resource code itself. (this publication can also be to be had in PDF softcopy from the OpenSPARC site, http://OpenSPARC.net)
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Additional info for OpenSPARC Internals
Example text
Strands are switched on a cycle-by-cycle basis between the available strands within the hard-partitioned group of four, using a least recently issued priority scheme. When a strand encounters a long-latency event, such as a cache miss, it is marked unavailable and instructions will not be issued from that strand until the long-latency event is resolved. Execution of the remaining available strands will continue while the long-latency event of the first strand is resolved. Each OpenSPARC T2 physical core has a 16-Kbyte, 8-way associative instruction cache (32-byte lines), 8-Kbyte, 4-way associative data cache (16byte lines), 64-entry fully-associative instruction TLB, and 128-entry fully associative data TLB that are shared by the eight strands.
Upon encountering a long latency instruction or other stall condition in a certain strand, the strand scheduler stops scheduling that strand for further execution. Scheduling commences again when the long latency instruction completes or the stall condition clears. FIGURE 4-3 illustrates the OpenSPARC T1 physical core. 2 OpenSPARC T1 Core Block Diagram Floating-Point Unit (FPU) A single floating-point unit is shared by all eight OpenSPARC T1 physical cores. The shared floating-point unit is sufficient for most commercial applications, in which fewer than 1% of instructions typically involve floating-point operations.
All traps are signaled in this stage. 1. Autodemap causes an existing TLB entry to be automatically removed when a new entry is installed with the same virtual page number (VPN) and same page size. 30 Chapter 4 OpenSPARC T1 and T2 Processor Implementations Instructions are classified as either short or long latency instructions. Upon encountering a long latency instruction or other stall condition in a certain strand, the strand scheduler stops scheduling that strand for further execution. Scheduling commences again when the long latency instruction completes or the stall condition clears.
OpenSPARC Internals by David L. Weaver
by Joseph
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