By Jean-Loup Baer
ISBN-10: 0521769922
ISBN-13: 9780521769921
This booklet offers a finished description of the structure of microprocessors from basic in-order brief pipeline designs to out-of-order superscalars. It discusses issues akin to - the guidelines and mechanisms wanted for out-of-order processing corresponding to sign up renaming, reservation stations, and reorder buffers - optimizations for top functionality akin to department predictors, guideline scheduling, and load-store speculations - layout offerings and improvements to tolerate latency within the cache hierarchy of unmarried and a number of processors - state of the art multithreading and multiprocessing emphasizing unmarried chip implementations issues are awarded as conceptual principles, with metrics to evaluate the functionality impression, if acceptable, and examples of cognizance. The emphasis is on how issues paintings at a black field and algorithmic point. the writer additionally offers adequate element on the sign in move point in order that readers can enjoy how layout beneficial properties increase functionality in addition to complexity.
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Sample text
3. Execute it. 4. Store the result and increment the program counter. In the case of a load or a store instruction, step 3 becomes two steps: calculate a memory address, and activate the memory for a read or for a write. In the latter case, no subsequent storing is needed. In the case of a branch, step 3 sets the program counter to point to the next instruction, and step 4 is voided. Early on in the design of processors, it was recognized that complete sequentiality between the executions of instructions was often too restrictive and that parallel execution was possible.
Assume that you have had some friends over for dinner and now it’s time to clean up. The first solution would be for you to do all the work: bringing the dishes to the sink, scraping them, washing them, drying them, and putting them back where they belong. Each of these five steps takes the same order of magnitude of time, say 30 seconds, but bringing the dishes is slightly faster (20 seconds) and storing them slightly slower (40 seconds). The time to clean one dish (the latency) is therefore 150 seconds.
Fortunately, the opportunity for such optimizations does not exist in the SPEC 2000 and 2006 benchmarks, because the number of instructions executed in each program is of the same order of magnitude. Nonetheless, the only faithful metric for execution times is the (weighted) arithmetic mean, and for rates it is the (weighted) harmonic mean. 2 Performance Simulators Measuring the execution time of programs on existing machines is easy, especially if the precision that is desired is of the order of milliseconds.
Microprocessor Architecture: From Simple Pipelines to Chip Multiprocessors by Jean-Loup Baer
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