By Nauman Khan
ISBN-10: 1461455073
ISBN-13: 9781461455073
This publication explores the demanding situations and provides most sensible ideas for designing Through-Silicon Vias (TSVs) for 3D built-in circuits. It describes a unique strategy to mitigate TSV-induced noise, the GND Plug, that's more advantageous to others tailored from 2-D planar applied sciences, corresponding to a bottom floor aircraft and conventional substrate contacts. The e-book additionally investigates, within the kind of a comparative learn, the effect of TSV dimension and granularity, spacing of C4 connectors, off-chip energy supply community, shared and devoted TSVs, and coaxial TSVs at the caliber of energy supply in three-D ICs. The authors supply targeted top layout practices for designing 3-D strength supply networks. on the grounds that TSVs occupy silicon real-estate and impression gadget density, this e-book offers 4 iterative algorithms to lessen the variety of TSVs in an influence supply community. in contrast to different current tools, those algorithms may be utilized in early layout levels while in simple terms sensible block- point behaviors and a floorplan can be found. ultimately, the authors discover using Carbon Nanotubes for strength grid layout as a futuristic replacement to Copper.
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Additional resources for Designing TSVs for 3D Integrated Circuits
Sample text
While each trace in the bin contains a unique power demand for each functional block (FB1-FB7), the relative power dissipation of functional blocks, in each trace, is similar (within ±5% variations). Relative power consumptions of the functional blocks determine the capability of the PDN to share power for neighboring functional blocks. For each bin, we simulate only the trace with the largest total power consumption; for example, trace 10 will be simulated representing the bin shown in Fig. 5.
These patterns were derived based on the work of Meeta et al. [42], where four SPEC workloads (apsi, bzip, equake, and mcf) were run for 100 million instructions using Wattch [21], and 2,048 cycle snippets (8,192 total traces) representing the current patterns were then extracted. Such a power grid evaluation methodology replaces observing millions of instructions from a wide variety of benchmarks, thus significantly saving power grid simulation times. 3 Optimal TSV Size for 3-D PDN We examine in this section how TSV size impacts 3-D power delivery.
Peak substrate noise decreases with increasing liner thickness. This trend is not uniform and can be divided into three segment. 1 and 1 μm, reduces for liner thickness between 1 and 2 μm, and saturates for thickness greater than 2 μm. • Peak substrate noise is ≈18% of VDD for liner thickness of 3 μm. 6 μm2 vs. 4 μm2 ). This huge area penalty, creates large interconnect blockages and reduces the area available for active devices. 2 Backside Ground Plane During assembly and packaging stages, a 2-D die is placed on a grounded metal layer.
Designing TSVs for 3D Integrated Circuits by Nauman Khan
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