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Read e-book online Current Trends in Hardware Verification and Automated PDF

By Avra Cohn (auth.), Graham Birtwistle, P. A. Subrahmanyam (eds.)

ISBN-10: 1461236584

ISBN-13: 9781461236580

ISBN-10: 1461281954

ISBN-13: 9781461281955

This document describes the partly accomplished correctness evidence of the Viper 'block model'. Viper [7,8,9,11,23] is a microprocessor designed by means of W. J. Cullyer, C. Pygott and J. Kershaw on the Royal indications and Radar institution in Malvern, England, (henceforth 'RSRE') to be used in safety-critical functions resembling civil aviation and nuclear strength plant keep an eye on. it's at present discovering makes use of in parts resembling the de­ ployment of guns from tactical airplane. To help safety-critical purposes, Viper has a particulary easy layout approximately which it really is fairly effortless to cause utilizing present thoughts and types. The designers, who deserve a lot credits for the promoting of formal equipment, meant from the beginning that Viper be officially proven. Their suggestion was once to version Viper in a chain of decreasingly summary degrees, each one of which targeting a few element ofthe layout, resembling the circulation ofcontrol, the processingofinstructions, and so forth. that's, each one version will be a specification of the subsequent (less summary) version, and an implementation of the former version (if any). The verification attempt may then be simplified by means of being dependent in response to the series of abstraction degrees. those types (or degrees) of description have been characterised by way of the layout workforce. the 1st degrees, and a part of the 3rd, have been written by means of them in a logical language amenable to reasoning and proof.

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Extra info for Current Trends in Hardware Verification and Automated Theorem Proving

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N. e_perform"sig n = ) /\ Un. n. e_iobar_sig n •... n. e_stepbar_sig n,e_reply_sig n») The memory, IIEIIORY_BLOCK, takes the five signals from the external interface and returns one signal to it: (e-data_in_sig). There is one latched signal, ram_sig, purely internal to the memory, representing the state of the memory. The only sub-function is IIEIIORY, which computes a new memory and data output based on the old memory and the inputs. 1- IIEIIORLBLOCK (e_data_out_sig ,e_address_sig, e_ io bar_sig.

8_iobar_sig n,e_data_out_sig n,8_address_sig n,8_strobebar_sig n, 8_writebar_sig n, ram_sig(n+t> ,e_data_in_sig n, minor_sig(n+O ,msjor_sig(n+O ,bflag_sig(n+O ,stop_sig(n+l) ,count_sig(n+l), alucon_s ig( n+l) ,bmplx_s ig(n+l) . tres_sig n,addr_sig n,inst_sig n. BLOCK_IEXT maps time-n values of states and inputs to the values of states and outputs as shown19 (that is, it sequences values correctly in time) if and only if the relation EXTERIAL_ARD_BLOCK_ARO_1IE1I holds over input, state and output signals.

E_iobar_sig n ,e_writebar_sig n. e_strobebar_sig n») 36 Blocks without latches are simpler. For example, as Figure 1 indicates, ALU_COKB has five inputs (two of them from D1TAREG) and two outputs (one of them to DATAREG). sig as above. The outputs are: the computed data output aoutbar_sig to DATAREG (as above); and a 9-bit word, conditions_sig, encoding certain facts, to BABDSTOP, as above. Without latches there are no internal lines to hide. The main function of the block is ALU. n. (aoutbar_sig n = FST(ALU(rbar_sig n,treg_sig n,cin_sig n,bflag_sig n,alucon_sig n») 1\ (conditions_sig n • SIOCALU(rbar_sig n,tras_sig n,cin_sig n,bflag_sig n,alucon_sig n»» Similarly, the TIllItG block has no latches.

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Current Trends in Hardware Verification and Automated Theorem Proving by Avra Cohn (auth.), Graham Birtwistle, P. A. Subrahmanyam (eds.)


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