By Gérard Berry (auth.), Laurence Pierre, Thomas Kropf (eds.)
ISBN-10: 3540481532
ISBN-13: 9783540481539
ISBN-10: 3540665595
ISBN-13: 9783540665595
CHARME’99 is the 10th in a sequence of operating meetings dedicated to the dev- opment and use of modern formal suggestions and instruments for the layout and veri?cation of and structures. earlier meetings were held in Darmstadt (1984), Edinburgh (1985), Grenoble (1986), Glasgow (1988), Leuven (1989), Torino (1991), Arles (1993), Frankfurt (1995) and Montreal (1997). This workshop and convention sequence has been equipped in cooperation with IFIP WG 10. five. it's now the biannual counterpart of FMCAD, which occurs each even-numbered 12 months within the united states. The 1999 occasion came about in undesirable Her- nalb, a lodge village situated within the Black woodland just about the town of Karlsruhe. The validation of practical and timing habit is a huge bottleneck in present VLSI layout structures. A predominantly educational region of research until eventually many years in the past, formal layout and veri?cation thoughts are actually migrating into business use. the purpose of CHARME’99 is to assemble researchers and clients from academia and operating during this energetic sector of analysis. invited talks illustrate significant present traits: the presentation via G´erard Berry (Ecole des Mines de Paris, Sophia-Antipolis, France) is anxious with using synchronous languages in circuit layout, and the controversy given through Peter Jansen (BMW, Munich, Germany) demonstrates an software of formal tools in an commercial surroundings. this system additionally contains 20 ordinary displays and 12 brief presentations/poster exhibitions which were chosen from the forty eight submitted papers.
Read Online or Download Correct Hardware Design and Verification Methods: 10th IFIP WG10.5 Advanced Research Working Conference, CHARME’99 BadHerrenalb,Germany,September 27–29, 1999 Proceedings PDF
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Extra info for Correct Hardware Design and Verification Methods: 10th IFIP WG10.5 Advanced Research Working Conference, CHARME’99 BadHerrenalb,Germany,September 27–29, 1999 Proceedings
Example text
V o _?? Fj ?? v ∧ v v x y v Fj o y Nj−1 Related Work Completion Functions The approach to correspondence checking proposed by Hosabettu et al. [19] replaces Burch & Dill’s flushing abstraction [4] with a composition of completion functions—each of which contains knowledge about how a pipeline stage behaves. For example, the abstraction function for a DLX pipeline [16] might be observem ◦ IF ID ◦ ID EX ◦ EX WB which results in the commuting diagram: @ABC GFED @ABC GFED @ABC /GFED / x2 / x3 x1 5= ID EX rr IF ID rr 5= r 5= r r r r r r r rrrr rrrrr rrrr nextm i rrrP1 rrP2 rrrP3 r r r r r r r rr rr u} rrrrr u} rrr u} rrrr @ABC GFED G @ABC FED G @ABC FED @ABC / / /GFED x x x a GFED @ABC a EX WB EX WB 1 ID EX 2 IF ID 3 observem GFED @ABC / b nextn i observem FED /G@ABC b P1, P2 and P3 assert properties about the effect that pipeline stages have on the implementation state.
1 Using Uninterpreted Next-State Relations When proving that holds for two state machines at level j ∈ {1 . . K}, we can use uninterpreted functions to represent the composition of levels 1 to j − 1. One caveat: the implementation transformer, Fj , must be monotonic. Proposition 2. ∀j ∈ {1 . . K} where Fj is monotonic with respect to (Mj−1 Nj−1 ) ∧ (Fj Nj−1 Gj Nj−1 ) ⇒ (Fj Mj−1 Gj Nj−1 ) Proof. By the monotonicity of Fj , and by the assumption that Mj−1 Fj Mj−1 Fj Nj−1 Fj Nj−1 Gj Nj−1 By assumption, Therefore, by the transitivity of , Fj Mj−1 Gj Nj−1 , Nj−1 , Formal Verification of Explicitly Parallel Microprocessors 31 Notice the subtle difference (of one letter) between Fj Nj−1 Gj Nj−1 and Fj Mj−1 Gj Nj−1 .
L. Pierre and T. ): CHARME’99, LNCS 1703, pp. 23–36, 1999. c Springer-Verlag Berlin Heidelberg 1999 24 Byron Cook et al. Speculative loads [8] behave like traditional loads—however exceptions are raised only when and only if the data they fetch is used. IA-64 and PARISC [21] both support speculative loading mechanisms. Multimedia instructions denote where optimizations specific to multimedia computation can be applied. MMX [3], AltiVec [13], and 3DNow [14,32] are examples of multimedia specific instruction-set extensions.
Correct Hardware Design and Verification Methods: 10th IFIP WG10.5 Advanced Research Working Conference, CHARME’99 BadHerrenalb,Germany,September 27–29, 1999 Proceedings by Gérard Berry (auth.), Laurence Pierre, Thomas Kropf (eds.)
by Ronald
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