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Download e-book for iPad: Computer- und Video-Spiele. Alles, was Eltern wissen sollten by Andrea M. Hesse; Harald Hesse

By Andrea M. Hesse; Harald Hesse

ISBN-10: 3776625406

ISBN-13: 9783776625400

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Example text

The only built-in primitives that can have more than one output port are the buf and not primitives, which can have many outputs, with the last terminal being the input. Example 3-1 Verilog Code for the 2-lnput and 4-lnput AND Gates and ( Y, A, B ) ; and ( Y, A, B, C, D ) ; All of the multiple-input primitives may have as many inputs as you need, so you could have a 100-input AND gate if you needed it. However, not all Verilog clone simulators support this. Ports in Modules Modules can have ports.

In more complex circuits, you can still use this technique to connect modules that contain constructs other than instances. HIERARCHICAL NAMES Figure 3-5, shows the 4-bit mux hierarchically expanded. There are four copies of the mux module. Each of the mux modules contains four gate instances, four ports, and three internal wires. Each of the four copies of the module has a unique Structural Modeling 25 hierarchical name. With hierarchical names, we can distinguish the copies so it is possible to uniquely identify each gate, port, and wire.

A hierarchical name can reference any object in a simulation. Hierarchical names have two forms: A downward path from the current module, or a name that starts at a top-level module and provides a complete path. ) to separate the elements in the path of a hierarchical name. Example 3-5 shows some hierarchical names. sel_n Connect by Name All of the hierarchy built by module instances in Example 3-3 and Example 3-4 are built by matching the port declaration order to the used to create the connections.

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Computer- und Video-Spiele. Alles, was Eltern wissen sollten by Andrea M. Hesse; Harald Hesse


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