By Michael J. Flynn
ISBN-10: 0867202041
ISBN-13: 9780867202045
Abstracts the fundamental parts of processor layout and emphasizes a layout technique together with layout strategies, layout aim info, and assessment instruments.
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Additional info for Computer architecture: pipelined and parallel processor design
Example text
Floating-point numbers have a number of different representations; the most common systems include those used in System 390, VAX, and the IEEE floating point standard [144]. Most floating-point numbers fit in either a word (32 bits, or short floating representation), or a 64-bit double word operand. Floating-point numbers contain a sign specification, a representation of the fraction (mantissa or significand), and the exponent representationeither exponent plus sign or a characteristic in an excess code representation.
10). 10 The R/M architecture. R/M format: one source operand may lie in memory, the other source operand must be a register that also serves as the destination (a two-address format, sometimes called one and one-half address because of the preceding limitation). Their format is Mem OP Mem � Mem. 10). The R/M architectures generally trace their evolution to the IBM System 360 introduced in 1963 (later System 370, the 3XXX models, Enterprise system, and S/390); there have been many variations on this basic architecture style.
Process of interpretation of generalized instructions can be slow (but R+M architectures make excellent use of memory/bus bandwidth). The L/S type of processor architecture uses fixed-size instructions (typically 32 bits) with uniform field interpretation (size typically 32 bits) and with a regular execution sequence. At the other extreme, the R+M architecture frequently uses compact and flexible representation of program actions. Instruction flexibility as represented by the R+M architecture provides a more compact representationfewer bits to fetch instructions for execution, fewer numbers of instructions to executewhile the more restrictive L/S architecture provides a more rapid execution of each instruction, but executes more instructions.
Computer architecture: pipelined and parallel processor design by Michael J. Flynn
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