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Extra resources for Complete digital design: a comprehensive guide to digital electronics and computer system architecture

Example text

In binary, the largest digit is 1, so any sum greater than 1 will result in a carry. The addition of 1112 and 0112 (7 + 3 = 10) is illustrated below. 1 + 1 1 1 0 1 1 1 0 1 1 0 1 0 carry bits In the first column, the sum of two ones is 210, or 102, resulting in a carry to the second column. The sum of the second column is 310, or 112, resulting in both a carry to the next column and a one in the sum. When all three columns are completed, a carry remains, having been pushed into a new fourth column.

12 CLOCK JITTER An ideal clock signal has a fixed frequency and duty cycle, resulting in its edges occurring at the exact time each cycle. Real clock signals exhibit slight variations in the timing of successive edges. This variation is known as jitter and is illustrated in Fig. 19. Jitter is caused by nonideal behavior of clock generator circuitry and results in some cycles being longer than nominal and some being shorter. The average clock frequency remains constant, but the cycle-to-cycle variance may cause timing problems.

Skew caused by wiring delay variance can be effectively minimized by designing a circuit so that clock distribution wires are matched in length. A more troublesome source of clock skew arises when there are too many clock loads to be driven by a single source. Multiple clock drivers are necessary in these situations, with small variations in electrical characteristics between each driver. These driver variances result in clock skew across all the flops in a synchronous design. As might be expected, clock skew usually reduces the frequency at which a synchronous circuit can operate.

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