By Kunle Olukotun
ISBN-10: 159829122X
ISBN-13: 9781598291223
ISBN-10: 1598291238
ISBN-13: 9781598291230
Chip multiprocessors - also referred to as multi-core microprocessors or CMPs for brief - at the moment are the one method to construct high-performance microprocessors, for quite a few purposes. huge uniprocessors aren't any longer scaling in functionality, since it is simply attainable to extract a constrained volume of parallelism from a customary guide movement utilizing traditional superscalar guide factor thoughts. moreover, one can't easily ratchet up the clock pace on trendy processors, or the facility dissipation turns into prohibitive in all yet water-cooled platforms. Compounding those difficulties is the straightforward incontrovertible fact that with the giant numbers of transistors to be had on modern day microprocessor chips, it truly is too expensive to layout and debug ever-larger processors each year or . CMPs keep away from those difficulties by way of filling up a processor die with a number of, particularly less complicated processor cores rather than only one large middle. the precise measurement of a CMPs cores can fluctuate from extremely simple pipelines to reasonably complicated superscalar processors, yet as soon as a middle has been chosen the CMPs functionality can simply scale throughout silicon strategy generations just by stamping down extra copies of the hard-to-design, high-speed processor middle in each one successive chip iteration. moreover, parallel code execution, acquired via spreading a number of threads of execution around the a number of cores, can in achieving considerably greater functionality than will be attainable utilizing just a unmarried middle. whereas parallel threads are already universal in lots of important workloads, there are nonetheless very important workloads which are not easy to divide into parallel threads. The low inter-processor conversation latency among the cores in a CMP is helping make a much broader diversity of purposes potential applicants for parallel execution than was once attainable with traditional, multi-chip multiprocessors; however, restricted parallelism in key functions is the most issue proscribing recognition of CMPs in a few sorts of platforms.
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Chip multiprocessors - also referred to as multi-core microprocessors or CMPs for brief - at the moment are the one option to construct high-performance microprocessors, for quite a few purposes. huge uniprocessors aren't any longer scaling in functionality, since it is barely attainable to extract a constrained quantity of parallelism from a standard guide flow utilizing traditional superscalar guideline factor concepts.
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Extra resources for Chip Multiprocessor Architecture: Techniques to Improve Throughput and Latency
Example text
Besides the obvious differences in instruction set architecture, frequency, and cache sizes, Niagara differs from Piranha by embracing multithreading. Each Niagara processor supports four threads in hardware, resulting in a total of 32 threads on the CPU. The Niagara processor employs fine-grain multithreading, and the processor hides memory and pipeline stalls on a given thread by scheduling the other threads in the group onto the pipeline with the zero-cycle switch penalty characteristic of fine-grain multithreading.
Each Rambus channel can support up to 32 RDRAM chips. In the 64 Mbit memory chip generation, each Piranha processing chip supports a total of 2 GB of physical memory (8 GB/32 GB with 256 Mb/1 Gb chips). 8 GB/s per processing chip. The latency for a random access to memory over the RDRAM channel book Mobk089 October 26, 2007 10:22 IMPROVING THROUGHPUT 29 is 60 ns for the critical word, and an additional 30 ns for the rest of the cache line. Unlike other Piranha chip modules, the memory controller does not have direct access to the intrachip switch.
The lower clock rate allows the design of a system with a significantly lower power supply voltage, often a nearly linear reduction. Since power is directly proportional to frequency and proportional to the square of the voltage, however, the power required to obtain the original performance is much lower—potentially as low as a quarter (half of the power due to the frequency reduction and one-half squared or a quarter of the power due to the voltage, for a total of one-eighth of the power per processor, so the power required for both processors together is one-quarter), although the potential savings will usually not quite achieve this level due to the limits of static power dissipation and any minimum voltage levels required by the underlying transistors.
Chip Multiprocessor Architecture: Techniques to Improve Throughput and Latency by Kunle Olukotun
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