By Woogeun Rhee (auth.), Arthur van Roermund, Michiel Steyaert, Johan H. Huijsing (eds.)
ISBN-10: 0306487071
ISBN-13: 9780306487071
ISBN-10: 1402075596
ISBN-13: 9781402075599
This ebook includes the contribution of 18 tutorials of the twelfth Workshop on Advances in Analog Circuit layout. it really is quantity 12 within the winning sequence of Analog Circuit layout, supplying beneficial details and ideal overviews of analog circuit layout, CAD, and RF structures. The sequence may be visible as a connection with these concerned about analog and mixed-signal layout.
Each publication discusses 3 particular issues on new and important layout principles within the zone of analog circuit layout. each one subject is mentioned through six specialists within the box and cutting-edge info is shared and overviewed. during this twelfth version the subjects are Fractional-N Synthesizers, layout for Robustness, and Line and Bus Drivers.
Analog Circuit Design is an important reference resource for analog layout engineers and researchers that desire to hold abreast with the newest advancements within the box. the academic insurance additionally makes it compatible to be used in a complicated layout direction.
Read Online or Download Analog Circuit Design: Fractional-N Synthesizers, Design for Robustness, Line and Bus Drivers PDF
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Extra resources for Analog Circuit Design: Fractional-N Synthesizers, Design for Robustness, Line and Bus Drivers
Example text
Table 1 describes the relationship between G(f) and its open loop counterpart, A(f). The open loop transfer function is, in turn, calculated from Figure 4 as specified in the table. Note that, throughout this document, we will switch between f, w, and s as the frequency variables of interest. In every case, we will assume that and s=jw. 31 Once the open loop transfer function is calculated, the last step in the design process is to realize an appropriate loop filter implementation. The methodology of doing so will be explained later in this document.
26 [17] [18] [19] [20] [21] [22] [23] [24] [25] [26] [27] [28] B. , May 2002, pp. 425-428. R. Ahola and K. Halonen, “A 2GHz fractional-N frequency synthesizer in CMOS,” in Proc. European Solid-State Circuits Conference, Sep. 2000, pp. 472-475. K. Chao, S. Nadeem, W. Lee, and C. Sodini, “A higher-order topology for interpolative modulation for oversampling A/D converters,” IEEE Transactions on Circuits and Systems, vol. 37, pp. 309-318, Mar. 1990. S. R. Norsworthy, R. Schreier, and G. C. Temes, Delta-Sigma Data Converters, Theory, Design, and Simulation.
3, a PFD topology as shown in Figure 19 [8], and a lead/lag filter that achieves an overall closed loop PLL bandwidth of 84 kHz. Both dynamic and noise simulations will include the noise sources depicted in Figure 22, with VCO noise being input referred as a white noise source as described in [14]. Parameters associated with the noise sources that are shown in the figure were computed from Hspice simulations and VCO measurements. 46 The simulation sample frequency was chosen as which is a factor of 20 higher than the reference frequency.
Analog Circuit Design: Fractional-N Synthesizers, Design for Robustness, Line and Bus Drivers by Woogeun Rhee (auth.), Arthur van Roermund, Michiel Steyaert, Johan H. Huijsing (eds.)
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