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Extra resources for 3D Stacked Chips: From Emerging Processes to Heterogeneous Systems

Example text

Wenzel from the Institute of Semiconductors and Microsystems, TU Dresden, for their assistance and hard work. Without their research, this project would have been impossible. References 1. W. Bartha, J. Greschner, M. Puech, Ph. Maquin, Low temperature etching of Si in high density plasma using SF6 =O2 . Microelectron. Eng. 27(1), 453–456 (1995) 2. F. Lärmer, A. Schilp, German patent no. 1994 3. L. Lai, D. Johnson, R. Westerman, Aspect ratio dependent etching lag reduction in deep silicon etch processes.

If this divider is switched on, the DC level can be adjusted by selectively switching the 4 PMOS transistors on or off via RSEL individually per link, which allows for a single VSSnoc to be used for multiple different links with different AC swings. The importance of proper DC level definition is demonstrated in Fig. 6. If the DC swing is either too low or too high, the data eye closes at receiver side and cannot be properly detected. Only an optimum calibration ensures equal eye width and height for both polarities.

The International Technology Roadmap for Semiconductors (ITRS) 2011 [18] defines a “3D-integration tech- J. de D. de M. de S. M. Elfadel, G. 1007/978-3-319-20481-9_3 29 30 J. Görner et al. 0 8 16 32 Physical Gate Length [nm] of predicted technology 64 Fig. 1 RC delay in (ps) for a 1mm wire on different interconnect-levels for different predicted Interconnect Technology Requirements based on data from the International Technology Roadmap for Semiconductors [14–19] for MPU/ASIC processes nology” for interconnects as a “via” technology that allows the stacking of basic circuit components in the third dimension, not only interconnect planes.

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